Do you know How LCD works?

Here the idea is to operate the display in serial mode.
You need several things for this: a video memory to store
the image, a means to send the image to the LCD several
dozen times per second (including driving Hsync, Vsync,
and the other signal lines), and some way to update the
data in the video memory. Discrete logic is normally used
for the latter two functions, but as regular readers of this
topic know, a lot of problems can be solved using an
AVR. In this project, we managed to ‘compact’ a whole
lot of electronics that would normally be implemented in
discrete logic into software running in an ATTiny2313.
The Tiny2313 is nice device, but the downside is that it
has only 15 I/O pins. This is nowhere near enough if you
want to use SRAM for the video memory. It takes a 16-kB
RAM chip just to feed a display with 320 × 240 pixels,
which means 14 lines for the address data alone, and
then you still need data lines, memory control lines, and
control lines for the LCD. This would make a larger AVR
necessary, but that’s not what you want.
Fortunately, there’s another way to tackle this problem by
using another type of RAM that is used much less often by
the average hobbyist: DRAM. The drawback of this sort
of RAM is that it must be refreshed continually. In addition,
it can’t be connected to a standard address bus. In
this application, neither of these drawbacks presents a
problem. If the DRAM is used as a video memory, it will
be read out (and thus refreshed) every 200 ms, and you
aren’t using a standard address bus here anyhow. (See
the inset ‘How DRAM works’ for a general explanation of
DRAM operation.)
Intelligent use
With a DRAM, you have to drive a total of eight address
lines plus a set data lines (four lines in this arrangement).
The two address bytes are latched on the falling edges
of RAS and CAS. This should mean that the address lines
can have any desired value when WE or OE goes low.
It’s thus possible to use the address lines for data, which
means you can omit the data lines. This reduces the total
number of multiplexed lines to eight (plus four control
lines). That’s not bad if you consider that you’re driving
64 kB with just 12 lines!
Naturally, the idea is to link all this to an LCD. A type that
can be used with this sort of circuit has at most eight data
lines, plus a line that marks the start of a frame (FLM), a
line that marks the start of a line (LP), a line for the sampling
clock (XSCL), and possibly some other stuff, such as
a display-enable line or a line that has to be toggled after
each frame. With a bit of luck, there will only be three
control lines, and even then it’s possible to combine one
of the signals with one of the RAM lines. This means you
need only 14 lines in total. If you use the last available
line as a serial port to write data to the RAM, you use all
the available ports of the ATTiny.